htw saar Piktogramm QR-encoded URL
Back to Main Page Choose Module Version:
XML-Code

flag

Computer Architecture

Module name (EN):
Name of module in study programme. It should be precise and clear.
Computer Architecture
Degree programme:
Study Programme with validity of corresponding study regulations containing this module.
Computer Science and Communication Systems, Bachelor, ASPO 01.10.2021
Module code: KIB-RA
SAP-Submodule-No.:
The exam administration creates a SAP-Submodule-No for every exam type in every module. The SAP-Submodule-No is equal for the same module in different study programs.
P222-0099, P222-0100
Hours per semester week / Teaching method:
The count of hours per week is a combination of lecture (V for German Vorlesung), exercise (U for Übung), practice (P) oder project (PA). For example a course of the form 2V+2U has 2 hours of lecture and 2 hours of exercise per week.
4V+1P (5 hours per week)
ECTS credits:
European Credit Transfer System. Points for successful completion of a course. Each ECTS point represents a workload of 30 hours.
5
Semester: 3
Mandatory course: yes
Language of instruction:
German
Assessment:


[still undocumented]
Applicability / Curricular relevance:
All study programs (with year of the version of study regulations) containing the course.

KIB-RA (P222-0099, P222-0100) Computer Science and Communication Systems, Bachelor, ASPO 01.10.2021 , semester 3, mandatory course
KIB-RA (P222-0099, P222-0100) Computer Science and Communication Systems, Bachelor, ASPO 01.10.2022 , semester 3, mandatory course
Workload:
Workload of student for successfully completing the course. Each ECTS credit represents 30 working hours. These are the combined effort of face-to-face time, post-processing the subject of the lecture, exercises and preparation for the exam.

The total workload is distributed on the semester (01.04.-30.09. during the summer term, 01.10.-31.03. during the winter term).
75 class hours (= 56.25 clock hours) over a 15-week period.
The total student study time is 150 hours (equivalent to 5 ECTS credits).
There are therefore 93.75 hours available for class preparation and follow-up work and exam preparation.
Recommended prerequisites (modules):
None.
Recommended as prerequisite for:
Module coordinator:
Prof. Dr.-Ing. Jürgen Schäfer
Lecturer:
Prof. Dr. Albrecht Kunz
Prof. Dr.-Ing. Jürgen Schäfer


[updated 25.01.2018]
Learning outcomes:
After successfully completing this module, students will be able to understand, analyze and design digital circuits (switching networks, switching devices). Important applications, especially from the field of computer technology, will be elaborated on and developed during this practical course.
 
Students will learn how digital computers are structured, organized and how they operate. The architectural elements of a computer will be discussed at register level and brought together to form a sample architecture. By understanding command processing, addressing techniques and concepts such as pipeline and cache, students will be able to understand modern computer architectures.


[updated 26.02.2018]
Module content:
Part I:
 1. Introduction
 2. Combinational circuits
  2.1 Basics
  2.2 Normal forms
  2.3 Minimization of switching functions
  2.4 Examples
 3. Sequential circuits
  3.1 Flip flops
  3.2 Registers, shift registers
  3.3 Counters
  3.4 Examples
 
Part II:
 1. Representing numbers in the computer
 2. Von Neumann architecture
 3. Memory components
 4. Sequential control
 5. Microprogramming
 6. Instruction set architecture
 7. Interrupt handling
 8. RISC processors
 9. Pipelining
10. Cache


[updated 26.02.2018]
Recommended or required reading:
Part I:
Borgmeyer: Grundlagen der Digitaltechnik, Hanser-Verlag, 2001
Borucki: Grundlagen der Digitaltechnik, Teubner-Verlag, 2000
Beuth: Digitaltechnik, Vogel Verlag, 2003
Urbanski: Digitaltechnik, Springer Verlag, 2004
 
Part II:
W. Schiffmann, R. Schmitz: Technische Informatik 2, Springer-Verlag, Berlin, 1999
K. Wüst, Mikroprozessortechnik, Vieweg-Verlag, Braunschweig, 2003
H. Malz, Rechnerarchitektur, Vieweg-Verlag, Braunschweig, 2004
J. L. Hennessy, D. A. Patterson: Rechnerarchitektur Analyse, Entwurf, Implementierung und Bewertung, Vieweg-Verlag, Braunschweig, 2004
P. Herrmann : Rechnerarchitektur _ Aufbau Organisation und Implementierung, Vieweg-Verlag, Braunschweig, 2000
 


[updated 26.02.2018]
Module offered in:
WS 2022/23, WS 2021/22, WS 2020/21, WS 2019/20, WS 2018/19 
[Sat Dec 28 10:15:49 CET 2024, CKEY=krb, BKEY=ki2, CID=KIB-RA, LANGUAGE=en, DATE=28.12.2024]