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Electronic Testing

Module name (EN):
Name of module in study programme. It should be precise and clear.
Electronic Testing
Degree programme:
Study Programme with validity of corresponding study regulations containing this module.
Electrical Engineering, Master, ASPO 01.10.2005
Module code: E933
Hours per semester week / Teaching method:
The count of hours per week is a combination of lecture (V for German Vorlesung), exercise (U for Übung), practice (P) oder project (PA). For example a course of the form 2V+2U has 2 hours of lecture and 2 hours of exercise per week.
2V (2 hours per week)
ECTS credits:
European Credit Transfer System. Points for successful completion of a course. Each ECTS point represents a workload of 30 hours.
2
Semester: 9
Mandatory course: no
Language of instruction:
German
Assessment:
Written examination

[updated 13.03.2010]
Applicability / Curricular relevance:
All study programs (with year of the version of study regulations) containing the course.

E933 Electrical Engineering, Master, ASPO 01.10.2005 , semester 9, optional course
Workload:
Workload of student for successfully completing the course. Each ECTS credit represents 30 working hours. These are the combined effort of face-to-face time, post-processing the subject of the lecture, exercises and preparation for the exam.

The total workload is distributed on the semester (01.04.-30.09. during the summer term, 01.10.-31.03. during the winter term).
30 class hours (= 22.5 clock hours) over a 15-week period.
The total student study time is 60 hours (equivalent to 2 ECTS credits).
There are therefore 37.5 hours available for class preparation and follow-up work and exam preparation.
Recommended prerequisites (modules):
None.
Recommended as prerequisite for:
Module coordinator:
Prof. Dr. Volker Schmitt
Lecturer:
Prof. Dr. Volker Schmitt


[updated 13.03.2010]
Learning outcomes:
Students will become acquainted with the problem and necessity of testing electronic circuits. Students will be taught the most common test procedures and will be able to design testable electronic circuits. They will also be able to decide on the most appropriate test method for a specific problem and to further their own understanding of other more specialist topics in electronic testing.

[updated 13.03.2010]
Module content:
- Introduction, verification, validation, identification
- Fault modelling, bonding faults, fault equivalence, fault dominance
- Test pattern generation, Boolean difference, path sensitization, the D-algorithm
- Fault simulation, methods, testability analysis, controllability,  
  observability, statistical techniques, estimation methods
- Design for testability
- Interrupt errors, delay faults, Reed-Muller form, test bus, self-testing  
  integrated circuits
- Test pattern generator, counters, linear and nonlinear feedback shift register,
  test data compression, signature analysis
- Boundary scan testing

[updated 13.03.2010]
Teaching methods/Media:
Overhead transparencies, master copies for photocopying

[updated 13.03.2010]
Recommended or required reading:
DAEHN, W.:  Testverfahren in der Mikroelektronik; Springer, 1997
AUER, A.; KIMMELMANN, R.:  Schaltungstest mit Boundary-Scan; Hüthig, 1996
Einführung in das Boundary-Scan Testverfahren; Hewlett Packard
HP Boundary-Scan Tutorial and BSDL Reference Guide; Hewlett Packard
The ABCs of Boundary-Scan Test; Philips


[updated 13.03.2010]
 
[Wed May  8 23:12:42 CEST 2024, CKEY=eta, BKEY=em, CID=E933, LANGUAGE=en, DATE=08.05.2024]